This invention relates generally to sample and hold circuits and particularly to sample and hold circuits having improved linearity.
As is known in the art, a sample and hold circuit includes a storage device, typically a capacitor, C.sub.h, coupled to an input signal V.sub.in to be sampled through a switch, S.sub.1 shown in FIG. 1. During the sampling, or tracking phase, switch S.sub.1 is "on" or "closed" and such "closed" switch S.sub.1 electrically connects the hold-capacitor C.sub.h to the input signal V.sub.in During the "hold" phase, the switch is "open" and hold-capacitor C.sub.h is electrically isolated from the voltage V.sub.in thereby storing, or holding, the last voltage of V.sub.in during the track phase. When implemented in Complementary Metal Oxide Semiconductor CMOS technology, as shown in FIG. 2, the switch S.sub.1 is implemented with MOS FET M.sub.1, here an NMOS FET and the control signal to open and close the switch S.sub.1 is fed to the gate as a voltage V.sub.g.
As is also known in the art, when the switch is implemented with a field effect transistor (FET), such transistor M.sub.1, here a PMOS FET, as shown in FIG. 3, has a channel in a semiconductor, a source region, S, in the semiconductor, a drain region, D, in the semiconductor a front-gate, FG, disposed over the channel, and a back-gate, BG, in the semiconductor under the channel. The front-gate FG and the back-gate BG are configured to control a flow of carriers in the semiconductor through a length of the channel between the source region, S, and the drain region, D. The capacitor C.sub.h is connected to one of the drain and source regions, here to the drain region, D. The other one of the source and drain region, here the source region, S, is configured for coupling to an input signal, V.sub.g. A switch, SW, is responsive to a sampling, or control signal, CS to electrically connect the front-gate FG to a constant potential V.sub.g during a tracking phase. (It should be understood that, as known in the art, the source and drain regions may be reversed in terminology and therefore, as is sometimes used herein, the term first region is used for one of the source and drain regions and the term second region is used for the other one of the source and drain regions. Thus, the front-gate and the back-gate are configured to control a flow of carriers through the channel between the first region and the second region).
During the tracking phase, the front-gate FG is coupled to V.sub.g, which is more negative than the voltage on the source S. Thus, the MOS FET M1 is biased "on" and C.sub.h is electrically connected to V.sub.in via a low impedance path through M.sub.1. During the hold phase, the front-gate FG voltage of M.sub.1 is biased 5 volts positive than the voltage on the source S. Thus the transistor M1 is "off", and C.sub.h is electrically isolated from V.sub.in.
As is also known, the "on" resistance of the field effect transistor (FET), that is, the resistance between the source region S and the drain region D when the transistor is "on`, or conducting, is a function of the front-gate-to-source voltage, V.sub.gs and the source-to-back-gate voltage V.sub.sb. Thus, the voltage sampled (i.e., stored) by the capacitor C.sub.h is a function of the "on" resistance. Consequently, the non-linearity in the `on" resistance produces a non-linearity in the circuit, i.e., the voltage stored is a non-linear function of the input signal V.sub.in. There have been several techniques suggested to reduce this non-linearity.
One technique uses CMOS FET devices (i.e., NMOS FET and PMOS FET) to cancel the non-linearities. Using this approach, the switch is implemented with a PMOS device in parallel with the NMOS device. The gate of the PMOS is driven by the logical complement of the signal used to drive the gate of the NMOS. By careful sizing of the PMOS device relative to that of the NMOS device, a reasonable degree of linearity can be achieved provided the logic levels (and the circuit's power supplies) are high enough in voltage. This technique however does not work well for low supply voltages (i.e., under 5 volts).
A second technique uses a boosted gate drive for driving a single FET. By increasing the front-gate voltage beyond the supply voltage during the "on" or tracking phase, the relative variation in V.sub.gs is reduced. This reduces the relative size of the switch's non-linearities. Such a circuit typically needs additional circuitry to generate on-chip voltages that are greater than the supply voltages. For low-voltage processes, these high voltages may reduce the product's reliability.
A third technique uses a bootstrapped gate drive for the switching device. By driving the front-gate of the switching transistor with a level shifted version of the signal that is applied to the switch's source, V.sub.gs is held constant. Since variations in V.sub.gs are the dominant source of non-linearity in the switching transistor, this approach greatly reduces the non-linearities of the switch. More particularly, reference is again to FIG. 3. Here, the switching transistor M.sub.1 has the substrate, more particularly the back-gate, BG, connected to VDD, the drain region, D, connected to the hold-capacitor C.sub.h and the front-gate FG connected to a switch SW. During the sample, or track phase, the switch SW connects the front-gate FG to a voltage V.sub.gs provided between the source S and front-gate FG, as indicated. During the hold phase, the switch connects the front-gate FG to VDD. While this circuit is typically implemented with an NMOS device as the switch S.sub.1, it is illustrated in FIG. 3 with a PMOS. Typically, the required V.sub.gs in this circuit is relatively large in order to achieve the desired linearity (i.e., to suppress the non-linearities due to variations in the source-to-back-gate voltage, V.sub.sb.
These techniques described above are suitable for reducing the transistor switch's non-linearities provided that the supply voltages are not too low, that the signal frequencies of interest are not too high, and that the substrate doping in the process is not too high. With the move to shorter channel process, the substrate doping is increased. The higher substrate doping causes the second term, V.sub.sb to have a larger impact on the transistor switch's non-linearity. When combined with the reduced power supplies, the switch non-linearities become unacceptable for many high frequency applications.